In recent years, considerable activity has been devoted to utilization of silicon as a substrate for mounting discrete integrated circuit devices and for interconnection of devices. This approach has been referred to by several names, including silicon multichip module, silicon-on-silicon, hybrid wafer scale integration, high-density multichip interconnect (HDMI), silicon interconnect substrate, etc. The approach involves the building up of layers of metal conductor lines and low dielectric constant polymers (e.g., polyimides) on a large silicon wafer substrate. The conductive traces provide interconnection between discrete integrated circuit devices (chips) which are mounted on top of those layers.
In this patent disclosure, the term "HDMI device" shall refer to the combination of a silicon substrate, polymer/metal interconnect layers, and integrated circuit devices (chips) mounted on those layers.
As with most integrated circuit devices, HDMI devices often are mounted in packages designed to hermetically protect the devices and to provide multiple electrical connections from the device to the outside world.
HDMI devices are typically designed to contain several chips mounted on multiple polymer layers on a large silicon substrate. The substrate is usually quite large (having lateral dimensions of about 1 to 4 inches). Additionally, the chips mounted on the upper surface create a topographically varying surface.
These features of HDMI devices create several packaging problems as compared to single chip packaging. Since the substrate is large, there is greater potential for build-up of stress due to differences in thermal expansion coefficient between the substrate and the base of the package. Thus, there is a greater need for the package base to have good thermal expansion match to silicon add high thermal conductivity. Thermal expansion matching to silicon is desired to prevent substantial stresses and mechanical failures upon heating (either during package assembly or actual operation of the device). High thermal conductivity in the package is highly desired since it also can help minimize development of stresses at the package-silicon interface by effective heat removal.
High flexural strength and Young's modulus are desired to prevent excessive flexing and breakage of the HDMI device in use. Additionally, a highly flat package base is desired to achieve good bonding across the large silicon substrate. Other advantages of a flat package base will be discussed below.
The package dielectric should have low dielectric constant and loss to prevent signal propagation delays in the conductive traces and cross-talk between neighboring conductors. Use of a good dielectric also gives the potential for multiple layers of conductive traces in the package.
The package must provide adequate means for input and output of electrical signals from the chips and layered interconnecting portions of the HDMI device to points outside the hermetically sealed area. For HDMI devices, high lead density often is required for perimeter-leaded packages (i.e. packages having leads located about the inside perimeter of the hermetically sealed area) because the multichip configuration greatly reduces the amount of available perimeter length per chip for location of lead pads.
In the past, perimeter-leaded package designs often suffered from a lack of hermeticity along the conductive paths formed from the perimeter leads to the exterior surface of the package base (i.e., outside the hermetically sealed zone). See FIG. 1 showing lead (8) traversing ceramic sealing portion (6) of package base (4). (Cover (3) and seal ring (2) are designed to seal the hermetic zone.) The lack of hermeticity is believed to be caused by a lack of sufficient bonding between the surface metallization forming the conductive path and the ceramic dielectric package base such that continuous cracks can be formed along this interface. This problem can be exacerbated in the event that poor chemical bonding occurs between the metallization and the ceramic base.
Other perimeter-leaded designs, such as shown in FIG. 2, involved construction of very elaborate vias (12) in the non-flat perimeter portions (16) of the package (14). (Seal ring 18 and cover 17 are designed to seal the hermetic zone.) Needless to say, such designs required more elaborate fabrication techniques. Neither of the prior art designs use a flat dielectric base, but rather both have elevated perimeter dielectric portions.
Packages having such non-flat dielectric bases often suffer from a lack of hermeticity in the dielectric base itself. Since non-flat bases usually have to be pressureless sintered, they have greater chance for delamination of the tape layers forming the base. Additionally, non-uniform bonding or shrinkage of tape layers can cause microcracking in the dielectric base. When these defects are present, there is a greater chance for formation of discontinuity paths in the package. Such discontinuity paths can destroy the hermeticity of the package by allowing contaminants such as water to migrate into the sealed zone.
For large packages (e.g., at least 2 inches.times.2 inches) designed to house HDMI devices, control of the dielectric base flatness to less than or equal to 0.001 inches deviation per inch of lateral position is desired to ensure good mechanical attachment of the substrate at the dielectric base. The very flat dielectric base and good mechanical contact provide a larger surface area of contact and therefore greater effective thermal conduction at the base-substrate interface. Pressureless sintering techniques typically result in about 0.002 inches/inch flatness which is inadequate for large packages. In addition, control of the positioning of ceramic and metal features co-fired in conventional sintering is typically limited to 0.25 to 0.5% of the lateral dimension of the package. For large packages, this limited precision places a lower limit on the attainable lead spacing, and therefore, an upper limit on the total number of lead pads (I/O's).
U.S. Pat. No. 4,920,640 offers an alternative approach to conventional co-firing by pressureless sintering. In this method, a uniaxial pressure is applied to the package preform during the high temperature densification process. This pressure effectively eliminates lateral shrinkage, thus providing much tighter control on the positioning of co-fired metal features. The applied pressure also serves to significantly decrease warpage in the fired part. This process has been demonstrated for co-firing of AlN with refractory metals.